Chapter 6
Video Display Boards and Controllers

What This Chapter is About

This chapter discusses video display hardware and relevant portions of the Video Electronics Standards Association (VESA) BIOS Extension (VBE) version 1.2 video controller programming specification. Readers desiring a more complete discussion should obtain a VBE specification package by contacting:

For VBE 1.2 compliant display controllers, VBE specifies standardized PC video interrupt (int 10h) extensions software exploits for video capabilities exceeding the original VGA hardware standard that only allowed screen resolutions of up to 640x480 with 16 colors. These Super VGA modes allow extended:

• Pixel colors
• Screen resolutions
• Frame buffer organizations

Video Board Architecture

Figure 6-1 is a high-level view depicting a typical video adapter hardware architecture containing:

• System bus connector
• Frame buffer memory
• Display controller containing:
  • a palette that describes 256 independent colors
  • an optional color ramp
  • a digital to analog converter (DAC)
• Video monitor connector

Figure 6-1  Typical video adapter hardware architecture

System Bus Connector

The system bus connector connects the video adapter to the system bus, allowing the system CPU to read and write frame buffer data. It also allows the CPU to manipulate display controller I/O registers to set different screen resolutions and frame buffer data interpretations.

Frame Buffer Memory

A CPU places data in frame buffer memory for display controller interpretation. The video display controller interprets frame buffer data depending on the system’s current video mode and correspondingly generates the correct video monitor signals based on frame buffer data and the video mode.

Frame buffer sizes vary from 256 KBytes to 4 MBytes (and beyond) of ordinary lower-cost Dynamic Random Access Memory (DRAM) or higher performance Video Random Access Memory (VRAM) that allows CPUs and display controllers to access a memory location simultaneously. Because with MS-DOS, only a maximum of 128 KBytes of the frame buffer memory is visible to the CPU at any one time, the CPU must perform frame buffer bank switching activities to gain access to the full memory space, 128 KBytes at a time. The Appendix A topic titled Frame Buffer Granule (Bank) Switching discusses this further.

Digital to Analog Converter (DAC)

The display controller DAC interprets digital frame buffer data in various ways to generate analog video display signals. This book only discusses two interpretation types:

• Packed pixel
• Direct color

In packed pixel interpretations, each display pixel corresponds to one, and only one, specific frame buffer data byte. Frame buffer data byte values are index values into a color list referred to as a palette. The CPU uses standard VGA video interrupts to set desired packed pixel screen resolutions and load palette data into some or all of the display controller’s 256 palette registers.

Each of the 256 independent palette registers holds three 1-byte values that completely describe one color that can appear on the screen in a packed pixel mode. It follows that packed pixel interpretation in combination with a specified screen resolution determines a specific video mode and that a CPU can load different values into the palette as required.

Because a byte can only hold one of 256 color values, a maximum of 256 colors from a possible 16,772,216 can simultaneously appear on display screens during packed pixel interpretation. For well-chosen colors, this is not a severe limitation and packed pixel images provide a natural compression advantage over direct color images.

Finally, software loads palette data into video controller hardware palettes using standard VGA int 10h requests. As the sample programs illustrate, pixel color information for each of the 256 colors often consists of 24 bits—8 bits describing a pixel’s red contribution, 8 bits describing the blue contribution, and 8 bits describing the green contribution. Due to a cruel original VGA programming legacy, software must reduce each component of each pixel to six bits with two-bit shift right operations before loading the information. This adjusts the 768 color component values (three components for each of 256 values) to the standard VGA’s, six-bit DAC width. Software can set some DAC widths to larger values, and VBE provides a way to detect this.

In direct color interpretations, each display pixel corresponds to two or more adjacent frame buffer data bytes. Typically, two, three, or four adjacent frame buffer bytes describe a given pixel. Some bits within the bytes may be reserved. At any instant, remaining bits are allocated in a fixed manner to the individual red, green, and blue color components. The bit allocation scheme and screen resolution uniquely determine direct color video modes which the CPU can set as needed.

Direct color interpretation allows video systems to display more simultaneous colors than packed pixel interpretation, but equivalent screen resolutions require more frame buffer memory (two, three, or four times as much) which may not be installed on a system’s particular video adapter. In such cases, while the display controller could theoretically provide a requested mode, the installed memory amount may preclude it.

Finally, display controllers may provide optional color ramp hardware for direct color video modes. Color ramp hardware allows display controllers to adjust display outputs rapidly by manipulating color ramp hardware rather than adjusting individual pixel frame buffer values. After determining the initial red, green, and blue signal strengths for each pixel, the display controller uses the color component signal strengths as an index into a CPU loaded table to determine the final signal strengths. While the table is a global table for the entire screen, it allows independent fine-tuning of the individual color components before screen display. This book does not discuss color ramps further.

Video Monitor Connector

The video monitor connector provides an attachment point for the monitor cable that carries display signals to the video display.